Obtaining electrical measurements from nodes of an electrical device via a capacitive sensing probe is often performed during the testing of a printed circuit board. As known in the art, capacitive sensing is a technique often used in determining the electrical connectivity of pins, nodes, traces, and other electrical conductors. See, for example, U.S. Pat. No. 5,696,431, Identification of Pin-Open Faults By Capacitive Coupling to Keirn et al., U.S. Pat. No. 5,498,964, Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies, to Kerschner et al., U.S. Pat. No. 5,254,953 to Crook et al., U.S. Pat. No. 5,241,336 to Crook et al., and U.S. Pat. No. 5,357,209 to Crook et al., all of which are incorporated by reference herein for all that they teach.
For purposes of clarity, the description herein will use the following terminology. As termed herein:
A “net” is an electrically conductive path between two endpoints.
A “test access point” or “test point” is a location on a printed circuit board where an external device (e.g., a probe) electrically physically contacts a point on a net.
A printed circuit board (PCB) “pad” is a location on a PCB where an integrated circuit lead or electrical component lead is electrically connected to the PCB. (The connection between the lead and pad is typically made via an integrated circuit/component pin that is connected to the pin within the integrated circuit/component package and solder between the pin and pad).
FIG. 1 shows a test configuration illustrating a prior art capacitive sensing technique for determining the integrity of the electrically connectivity of an integrated circuit pin to a net. As illustrated, the test configuration utilizes a capacitive sensing probe 2. The capacitive sensing probe 2 includes a metallic electrode that is positioned over the integrated circuit package 4 of an integrated circuit in close proximity to a lead conductor 7 that is connected to an integrated circuit pin 6 inside the integrated circuit package 4. An oscillator 8 supplies an alternating current signal, typically eight kilohertz (8 KHz) at 100 mV. The output of the oscillator 8 is connected to a net 12 (which may be a wire, a trace, a solder bump, or any other known conductive material, and/or combination thereof) at a first end 12a. The net 12 is connected at a second end 12b to the integrated circuit pin 6, which is connected to lead conductor 7.
To perform a test, the integrated circuit pin 6 is stimulated (through net 12) by the AC signal generated by the oscillator 8. If the net 12 between end 12a at the output of the oscillator 8 and end 12b at the integrated circuit pin 6 is electrically intact, and the net 12 is electrically connected to the pin 6, the AC signal applied at the first end 12a of the net 12 will appear on the integrated circuit pin 6 and conductive lead 7, where it will be capacitively coupled through the integrated circuit package to the capacitive sensing probe 2. The capacitive sensing probe returns the capacitively coupled signal to a measurement circuit 14. The measurement circuit 14 includes a phase synchronous voltmeter 10 that receives the AC source signal 5 from the oscillator 8 and the capacitively coupled signal 3 from the probe 3. The phase synchronous voltmeter 10 attempts to phase synchronize the capacitively coupled signal 3 with the AC source signal 5. The voltmeter 10 measures not only the amplitude of the capacitively coupled signal 3 from the probe 3 but also its phase relative to the source signal 5. The voltmeter rejects noise by integrating the signal over multiple cycles of the source frequency. Phase information is used to differentiate between capacitive, resistive, and inductive impedances.
If the amplitude of the measured impedances falls within a predetermined acceptable range (as calculated based on the board design or as obtained from measurements from a known good board), the integrated circuit pin 6 is considered to be properly electrically connected (e.g., soldered, wire-bonded, etc.).
Open circuits are a common defect in the manufacture of PCB assemblies, typically occurring as a result of poor solder bonds, incomplete traces, and/or missing devices that are either never loaded onto the board or which fall off during the assembly process. The capacitive sensing technique is often used in PCB testers for detecting open connections on a PCB assembly. A PCB tester typically includes a number of tester interface pins that are arranged on a face of the tester in a predefined configuration. Because the positions of the tester interface pins are unchangeable, a test fixture customized to the particular design of the PCB under test is typically required to interface between the tester interface pins of the tester and test points on the PCB under test. The test fixture includes circuitry (e.g., wires, probes) that electrically connects various tester interface pins on the tester to various test access points on the PCB under test.
Test access points of interest may be stimulated by an AC source in the tester. In this regard, the AC source in the tester may be connected to various tester interface pins via configurable relays within the tester. Thus, stimulation of a given test access point may therefore be achieved by configuring the relays to connect the AC source to a given tester interface pin that connects to the test access point of interest on the PCB via the test fixture. By design, the test access point on a PCB should be connected to a component under test (e.g., and integrated circuit pin) via a net. The electrically integrity of the net and net-to-component connection may be tested by using the capacitive sensing technique previously described.
In large testers, the number of available AC reference sources may be limited. Thus, testing of a complete PCB may require many relay configuration cycles in order to connect each of the nets under test to an available AC source. As known in the art, the relay configuration and settling time can take a significant amount of time relative to the time required to obtain the capacitively coupled measurement. Since a PCB can contain hundreds or thousands or more nets and net-to-component connections to be tested, this relay configuration procedure can prove to be too costly in terms of test time when only a limited number of AC sources are available for net stimulation.
It will be recognized that although the availability of many, or even multiple, AC sources in a large tester is often limited or non-existent, in such testers there is often a proliferation of digital sources available due to the use of the tester in performing digital functional tests. When configuring the tester for digital functional test, the tester often has the ability to connect all or many of its tester interface pins to a corresponding digital source in the tester in a nearly one-to-one mapping. Thus, all relay connections could be performed in parallel and the configuration time could be reduced to the relay settling time of the slowest relay if the digital sources could be used in place of the AC source(s) of the tester. However, because the digital sources generate no phase information, in the past digital sources have not been used to obtain capacitively sensed measurements because the digital sources cannot be phase synchronized with the capacitively coupled signal. It would therefore be desirable to have a method that would allow the use of ubiquitously available digital sources in a printed circuit board tester to allow faster acquisition of multiple capacitively sensed measurements.